Abstract
TRACK 1-1
Calibre Overall Solutions at TSMC Advanced Nodes
Mentor: Shu-Wen Chang, Director, Calibre Foundry Programs
TSMC Co-Presenter: Peter Hsu, Section Manager for TSMC Design Methodology
Calibre Overall Solutions at TSMC Advanced Nodes: Calibre platform is the golden sign off solution in TSMC Physical verification flow . In this session , we will co-present with TSMC to talk about what you should know at TSMC advanced nodes and why Calibre solutions are must be used .
TRACK 1-2
Competing in Reliability Focused Growth Markets with Calibre PERC
Mentor: Yi-Ting Lee, Foundry Technical Lead
With the growing demand for smart, connected functionality in large markets such as consumer, automotive safety, navigation, infotainment, commercial aviation, and medical, designers (and foundries) are entering a new era of IC reliability verification. Improving IC reliability requires a specific mindset and focus, and a different type of IC verification than we have been using in the past. Designers often find reliability checks difficult or impossible to implement using the traditional DRC, LVS and ERC verification tools. Validating that designs are robust over time, that they will age gracefully, and will fail in a known way are key criteria for device acceptance in this new era of reliability-focused verification. This session describes how Calibre® PERC™ can help you be successful by providing a comprehensive platform to address a wide range of reliability focused challenges.
TRACK 1-3
Calibre: We've Already Got you Covered for 10nm
Mentor: David Abercrombie, DFM Program Manager
As you would expect the Calibre nm Platform is already prepared for 10nm and in fact is already working on 7nm. Come learn how physical verification is changing at 10nm and how we already have the golden sign-off solutions to ensure your design is ready for tape out.
TRACK 1-4
Meeting New Extraction Challenges at Advanced Nodes and Advanced Designs
Mentor: Myron Lin, Senior Foundry Technical Lead
Circuit designers have to wrestle with performance versus accuracy tradeoffs throughout the design cycle. Parasitic extraction is no different. At the leading process nodes using more complex FinFET devices, design engineers are pushing for tighter accuracy, while also needing higher performance and capacity for billion transistor designs. Additionally, different design styles, such as memory, analog, standard cell, and custom digital, pose different challenges for extraction tools. To meet these requirements, Mentor developed a new extraction product from the ground up for advanced ICs. Calibre xACT has unique modeling capability for FinFET based processes but is also applicable for traditional MOSFETs as well. Calibre xACT uses a combination of compact model, field solver and efficient multi-CPU scaling technologies to ensure robust accuracy as well as turnaround performance needed to meet schedule deadlines.
TRACK 2-1
Silicon diagnosis and yield analysis in the FinFET era
Mentor: Geir Eide, Product Marketing Manager
Achieving desired failure analysis success rates and turn-around time isbecoming increasingly challenging as designs grow in complexity and feature sizes shrink. It is crucial to be able to focus resources on the most relevant failing devices. In this presentation, you will learn about the most recent advancements in diagnosis technology such as transistor-level diagnosis and statistical enhancement techniques that improve the resolution of diagnosis results. With this latest technology, it is possible to focus the failure analysis efforts on the biggest yield hitters, and dramatically improve time to root cause.
TRACK 2-2
Saving time and cost of your FinFET designs through truly integrated hierarchical DFT solution
Mentor: Fangin Meng, Sr. Application Engineer
Spreadtrum Co-Presenter: Kenneth Huang, DFT Flow Manager
TRACK 2-3
The Internet of Things(IoT) and Increased Design Complexity in Established Nodes
Mentor: Michael Buehler-Garcia, Marketing Director
Our love of ever more interconnected and capable electronic products is both increasing the design complexity and extending the economic life of established nodes (e.g. 180nm, 90nm, …, 28nm). The increase in design complexity brings new physical verification challenges not seen when these processes where first created. Come learn about the solutions available from the Calibre platform.
TRACK 2-4
DRC-Clean Cell Design in 30 minutes- Qualcomm’s Experience with Calibre RealTime
Qualcomm: Tom Williams, Custom Design Lead
Converging to a DRC-clean design is becoming more complex and time-consuming, causing significantly increased time to reach final tape-out. In this session you will see how Qualcomm used Calibre RealTime in their design environment to reduce the DRC-clean cycle time from half a day to 30 minutes for their typical standard cell, while learning the new technology node rules. The focus will be on how Calibre RealTime enabled designers to tighten bus signals, preferred metal direction routes, clean up base layers, handle the coloring loops and quickly fix top-level DRC errors.
TRACK 3-1
Enterprise Verification: Productivity from Formal - Simulation – Emulation
Mentor: Stewart Li, Sr. AE Consultant
We live in a System on Chip world that not only makes existing verification challenges more difficult, but also introduces new challenges altogether. This presentation will show how Mentor Graphics’ Enterprise Verification Platform offers faster, stronger, and smarter verification for IP block, sub-system, and full system levels of the current generation and next-generation of SoC designs.
TRACK 3-2
Veloce - the Technology Leader in Emulation
Mentor: Samuel Wu, Sr. Application Engineer
Emulation is a really hot topic these days. Its popularity is a result of numerous factors, including record-breaking design capacity, increased speed of execution, and improved functionality. These days, hardware designers and verification engineers aren’t the only ones using emulation. Software programmers are using it as well to validate embedded software –– applications, diagnostics, drivers, operating systems and software-driven tests, all with a need to process hundreds of billions of cycles –– extending its use across the entire SoC development cycle. Now considered among the most versatile and powerful of verification tools, project teams also use it for hardware debugging, hardware/software co-verification or integration, system-level prototyping, low-power verification and power estimation and performance characterization. This session looks at why the Veloce Emulation platform is the technology leader in an area that continues to grow at record pace.
TRACK 3-3
EZ Design and Verification of AMBA® Based Designs
Mentor: Adam Rose, Principal Verification Technologist
ARM Co-Presenter: David Hsu, FAE Manager
Today's market calls for the creation of highly complex designs within short schedules, leading to numerous challenges in both design and verification. This presentation from ARM® and Mentor Graphics shows how these challenges have been overcome by combining the latest design and verification IP for a complete verification flow from system level modelling, through simulation, emulation and FPGA prototyping. Expect to learn about the latest easy-to-use VIP from Mentor for ARM® AMBA® protocols and the latest ARM® IP and tools, along with how they can be used together for a complete design and verification solution.
TRACK 3-4
Project Nitro – Mentor’s Next Generation Place and Route System
Mentor: Siegfried Wang, Deployment & Foundries Manager
This session will highlight Mentor's next generation Place and Route system – Project Nitro. Some of the key and unique technologies of this advanced place and route system that will be covered include faster throughput of up to 2M instances/day, new compact database for handling large block sizes (5M instances), comprehensive power reduction capabilities for FinFET nodes, superior QoR for power, area, performance, complete abutted floorplanning support and area reduction and direct interface to Calibre to handle complex DRC/DFM/Double Patterning requirements for smaller nodes.
TRACK 4-1
Accurate nm Circuit Verification and Device Noise Analysis of Analog/Mixed-Signal ICs
Mentor: Greg Curtis, Product Marketing Manager
Analog/mixed-signal design teams in FinFET process nodes face significant challenges in meeting their performance and power specs as a result of increased parasitics, device noise, voltage scaling, and process variation effects. This session provides details on how the Analog FastSPICE (AFS) Platform addresses these challenges. Foundry certified to 10nm FinFET-based processes, the AFS Platform delivers nanometer SPICE accuracy 5x-10x faster than traditional SPICE and 2x-6x faster than parallel SPICE simulators on circuits up to 10 Million elements and includes the industry’s only full-spectrum, device noise analysis.
TRACK 4-2
How to Customize and Further Leverage your Calibre Licenses
Mentor: Leo Chang, Team Lead
Beyond standard physical verification usage, you can implement other useful applications using a variety of Calibre features. This session starts with illustrating how to use Calibre to do Layout Manipulation and Layout Analysis. Then we’ll show you how to assemble these features of Calibre to build complete flows: Automation of Adding Customized Patterns Along Cell/Chip Boundaries, Pattern Library Maintenance, and Chip Device Parameter Analysis. Come and learn real examples of creatively using Calibre and get inspired to apply more Calibre features in your design flow.
TRACK 4-3
Optimized Co-design of an IC / Package / PCB System
Mentor: Jamie Metcalfe, Market Development Manager
Design of an IC/package/PCB system is typically done in isolated, disconnected stages resulting products with higher cost and lower performance. This session will introduce a new solution to automate planning and assembly of today’s complex multi-die packages. It ensures that ICs, packages and PCBs are optimized with each other to reduce package substrate and PCB costs by efficient layer reduction, optimized interconnect paths, and streamlined/automated control of the design process.
TRACK 4-4
Accelerated, Accurate Electromagnetic Modeling of IC Packages
Mentor: Jamie Metcalfe, Market Development Manager
Modeling and simulation of an IC/package/PCB system often requires extensive modeling expertise and a lifetime to wait for results. This session will address an alternative process that accurately and quickly models complex package structures using a combination of 3D full-wave analysis with quasi-static extraction to create a hybrid model for simulation of system signal and power integrity.